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INTEGRATED CIRCUITS
DATA SHEET
UMA1015AM Low-power dual frequency synthesizer for radio communications
Product specification Supersedes data of 1997 Jun 10 File under Integrated Circuits, IC17 1997 Sep 03
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
FEATURES * Two fully programmable RF dividers up to 1.1 GHz * Fully programmable reference divider up to 35 MHz * 2 : 1 or 1 : 1 ratio of selectable reference frequencies * Fast three-line serial bus interface * Adjustable phase comparator gain * Programmable out-of-lock indication for both loops * On-chip voltage doubler * Low current consumption from 3 V supply * Separate power-down mode for each synthesizer * Up to 4 open-drain output ports * Crystal input frequency signal inverted and buffered output on separate pin. APPLICATIONS * Cordless telephone * Hand-held mobile radio. QUICK REFERENCE DATA SYMBOL VDD1, VDD2 VCC VCCvd PARAMETER digital supply voltage CONDITIONS VDD1 = VDD2 MIN. 2.7 2.7 - - - - 50 3 - - -30 - - GENERAL DESCRIPTION
UMA1015AM
The UMA1015AM is a low-power dual frequency synthesizer for radio communications which operates in the 50 to 1100 MHz frequency range. Each synthesizer consists of a fully programmable main divider, a phase and frequency detector and a charge pump. There is a fully programmable reference divider common to both synthesizers which operates up to 35 MHz. The device is programmed via a 3-wire serial bus which operates up to 10 MHz. The charge pump currents (gains) are fixed by an external resistance at pin 20 (ISET). The BiCMOS device is designed to operate from 2.7 V (3 NiCd cells) to 5.5 V at low current. Digital supplies VDD1 and VDD2 must be at the same potential. The charge pump supply (VCC) can be provided by an external source or on-chip voltage doubler. VCC must be equal to or higher than VDD1. Each synthesizer can be powered-down independently via the serial bus to save current. It is also possible to power-down the device via the HPD input (pin 5).
TYP.
MAX. UNIT 5.5 6.0 V V V mA A mA MHz MHz kHz kHz C
charge pump supply voltage external supply; doubler disabled; VCC VDD charge pump supply from voltage doubler doubler enabled both synthesizers ON; doubler disabled; VDD1 = VDD2 = 3 V doubler disabled; VDD1 = VDD2 = 3 V
2VDD1 - 0.6 6.0 8.7 3 0.25 - - 10 750 - - - - 1100 35 - - +85
IDD1 + IDD2 + ICC operating supply current IDDpd + ICCpd IDDpd fRF fXTALIN fpc(min) fpc(max) Tamb total current in power-down mode
current in power-down mode doubler enabled; from supply VDD1 and VDD2 VDD1 = VDD2 = 3 V RF input frequency for each synthesizer crystal input frequency minimum phase comparator frequency maximum phase comparator frequency operating ambient temperature
1997 Sep 03
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Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UMA1015AM BLOCK DIAGRAM SSOP20 DESCRIPTION
UMA1015AM
VERSION SOT266-1
plastic shrink small outline package; 20 leads; body width 4.4 mm
handbook, full pagewidth
VDD1 4
VDD2 14
DGND 7
AGND 16
ISET 20
VCC 18
CLK DATA
11 12 4-BIT SHIFT REGISTER 17-BIT SHIFT REGISTER PUMP BIAS CONTROL LATCH VOLTAGE DOUBLER
E
13
ADDRESS DECODER power OOL current down select ratio port bits
VDB enable RF/64
LATCH RFA 6 MAIN DIVIDER TOOL A HPD 5 RFA/64 LOCK DETECTOR phase error PHASE DETECTOR 3 CPA
SYNTHESIZER A
10 fXTALO fXTALIN 8 LATCH REFERENCE DIVIDER DIV BY 2 SR
TOOL A LOCK SELECT TOOL B 19 1 2 9
P0/OOL P1 P2 P3
UMA1015AM
SYNTHESIZER B
LATCH RFB 15 MAIN DIVIDER TOOL B RFB/64
LOCK DETECTOR
phase error
PHASE DETECTOR
17
CPB
MGG523
Fig.1 Block diagram.
1997 Sep 03
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Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
PINNING SYMBOL P1 P2 CPA VDD1 HPD RFA DGND fXTALIN P3 fXTALO CLK DATA E VDD2 RFB AGND CPB VCC P0/OOL ISET PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION output Port 1 output Port 2 charge pump output synthesizer A digital supply voltage 1 hardware power-down (input LOW = power-down) RF input synthesizer A digital ground common crystal frequency input from TCXO output Port 3 open-drain output of fXTAL signal programming bus clock input programming bus data input programming bus enable input (active LOW) digital supply voltage 2 RF input synthesizer B analog ground to charge pumps charge pump output synthesizer B analog supply to charge pump; external or voltage doubler output Port output 0/out-of-lock output regulator pin to set charge pump currents
CPA VDD1 HPD RFA DGND fXTALIN P3
handbook, halfpage
UMA1015AM
P1 P2
1 2 3 4 5
20 ISET 19 P0/OOL 18 VCC 17 CPB 16 AGND
UMA1015AM
6 7 8 9 15 14 13 12 RFB VDD2 E DATA
fXTALO 10
MGG522
11 CLK
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION Main dividers Each synthesizer has a fully programmable 17-bit main divider. The RF input drives a pre-amplifier to provide the clock to the first divider bit. The pre-amplifier has a high input impedance, dominated by pin and pad capacitance. The circuit operates with signal levels from below 50 mV (RMS) up to 250 mV (RMS), and at frequencies up to 1.1 GHz. The high frequency sections of the divider are implemented using bipolar transistors, while the slower section uses CMOS technology. The range of division ratios is 512 to 131071. Reference divider There is a common fully programmable 12-bit reference divider for the two synthesizers. The input fXTALIN drives a pre-amplifier to provide the clock input for the reference 1997 Sep 03 4
divider. This clock signal is also inverted and output on pin fXTALO (open drain). A crystal connected between fXTALIN and fXTALO with suitable feedback components can be used to make an oscillator. An extra divide-by-2 block allows a reference comparison frequency for synthesizer B to be half the frequency of synthesizer A. This feature is selectable using the program bit SR. If the programmed reference divider ratio is R then the ratio for each synthesizer is as given in Table 1. The range for the division ratio R is 8 to 4095. Opposite edges of the divider output are used to drive the phase detectors to ensure that active edges arrive at the phase detectors of each synthesizer at different times. This minimizes the potential for interference between the charge pumps of each loop. The reference divider consists of CMOS devices operating beyond 35 MHz.
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
Table 1 SR 0 1 Phase comparators For each synthesizer, the outputs of the main and reference dividers drive a phase comparator where a charge pump produces phase error current pulses for integration in an external loop filter. The charge pump current is set by an external resistance RSET at pin ISET, where a temperature-independent voltage of 1.1 V is generated. RSET should be between 12 and 60 k. The charge pump current, ICP, can be programmed to be either (12 x ISET) or (24 x ISET) with a maximum of 2.3 mA. The dead zone, caused by finite switching of current pulses, is cancelled by an internal delay in the phase detector thus giving improved linearity. The charge pump has a separate supply, VCC, which helps to reduce the interference on the charge pump output from other parts of the circuit. VCC can be higher than VDD1 if a wider range on the VCO input is required. VCC must not be less than VDD1. Voltage doubler If required, there is a voltage doubler on-chip to supply the charge pumps at a higher level than the nominal available supply. The doubler operates from the digital supply VDD1, and is internally limited to a maximum output of 6 V. An external capacitor is required on pin VCC for smoothing, the capacitor required to develop the extra voltage is integrated on-chip. To minimize the noise being introduced to the charge pump output from the voltage doubler, the doubler clock is suppressed (provided both loops are in-lock) for the short time that the charge pumps are active. The doubler clock (RF/64) is derived from whichever main divider is operating (synthesizer A has priority). While both synthesizers are powered down (and the doubler is enabled), the doubler clock is supplied by a low-current internal oscillator. The doubler can be disabled by programming the bit VDON to logic 0, in order to allow an external charge pump supply to be used. Out-of-lock indication/output ports There is a common lock detector on-chip for the synthesizers. The lock condition of each, or both loops, is output via an open-drain transistor which drives pin P0/OOL (when out-of-lock, the transistor is turned on and therefore the output is forced LOW). The lock condition output is software selectable (see Table 4). Synthesizer ratio of reference divider SYNTHESIZER A R R SYNTHESIZER B R 2R
UMA1015AM
An out-of-lock condition is flagged when the phase error is greater than TOOL, which is approximately 30 ns. The out-of-lock flag is only released after the first reference cycle where the phase error is less than TOOL. The out-of-lock function can be disabled, via the serial bus, and the pin P0/OOL can be used as a port output. Three other port outputs P1, P2 and P3 (open-drain transistors) are also available. Serial programming bus A simple 3-line unidirectional serial bus is used to program the circuit. The 3 lines are DATA, CLK and E (enable). The data sent to the device is loaded in bursts framed by E. Programming clock edges are ignored until E goes active LOW. The programmed information is loaded into the addressed latch when E returns inactive (HIGH). This is allowed when CLK is in either state without causing any consequences to the register data. Only the last 21 bits serially clocked into the device are retained within the programming register. Additional leading bits are ignored, and no check is made on the number of clock pulses. The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new programming data even during power-down of both synthesizers. However when either synthesizer A or synthesizer B or both are powered-on, the presence of a TCXO signal is required at pin 8 (fXTALIN) for correct programming. Data format Data is entered with the most significant bit first. The leading bits make up the data field, while the trailing four bits are an address field. The address bits are decoded on the rising edge of E. This produces an internal load pulse to store the data in the addressed latch. To ensure that data is correctly loaded on first power-up, E should be held LOW and only taken HIGH after having programmed an appropriate register. To avoid erroneous divider ratios, the pulse is inhibited during the period when data is read by the frequency dividers. This condition is guaranteed by respecting a minimum E pulse width after data transfer. The data format and register bit allocations are shown in Table 2.
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Philips Semiconductors
Table 2 FIRST p1 dt16 X MA16 0 MB16 0 Note
Bit allocation
Low-power dual frequency synthesizer for radio communications
REGISTER BIT ALLOCATION p2 X 0 p3 p4 p5 p6 p7 p8 p9 p10 X p11 p12 p13 dt4 sPDA sPDB P3 p14 dt3 P2 p15 dt2 P1 p16 dt1 X p17 dt0 X MA0 R0 MB0 0 0 sPBF 0 0 0 0 0 0 0 0 1 p18 p19 0 1 1 1 0 0 p20 0 0 0 1 0 0 dt15 dt14 dt13 dt12 DATA FIELD SYNTHESIZER A MAIN DIVIDER COEFFICIENT 0 0 SR R11 REFERENCE DIVIDER COEFFICIENT RESERVED FOR 0 0 0 0 0 0 0 0 0 TEST(1) 0 SYNTHESIZER B MAIN DIVIDER COEFFICIENT ADDRESS
LAST p21 1 0 1 0 0 0
VDON PO
OLA OLB CRA CRB X
1. The test register should not be programmed with any other values except all zeros for normal operation. Table 3 Bit allocation description DESCRIPTION software power-down for synthesizers A and B (0 = power-down) software power-on for fxtal buffer (1 = buffer on) bits output to pins 1, 2, 9 and 19 (1 = high impedance) voltage doubler enable (1 = doubler enabled) out-of-lock select; selects signal output to pin 19 (see Table 4) charge pump A/B current to ISET ratio select (see Table 5) reference frequency ratio select (see Table 6) Out-of-lock select OLA 0 0 1 1 OLB 0 1 0 1 P0 lock status of loop B; OOLB lock status of loop A; OOLA logic OR function of loops A and B OUTPUT AT PIN 19
SYMBOL sPDA, sPDB sPBF P3, P2, P1 and P0 VDON OLA, OLB CRA, CRB SR Table 4
UMA1015AM
Product specification
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
Table 5 Charge pump current ratio CURRENT AT PUMP ICP = 12 x ISET ICP = 24 x ISET Reference division ratio SYNTHESIZER A R R SYNTHESIZER B R 2R
UMA1015AM
The synthesizers are powered up when both hardware and software Power-down signals are at logic 1. When only one synthesizer is powered down, the functions common to both will be maintained (independent of the state of sPBF). When both synthesizers are powered down, the fxtal buffer can be maintained in an active state by setting sPBF to logic 1. This will allow any system clock derived from the fXTALO buffered output to remain on in power-down. Note that sPBF is independent of the state of HPD. When both synthesizers are switched off, the voltage doubler (if enabled) will remain active drawing a reduced current. An internal oscillator will drive the doubler in this situation. If both synthesizers have been in a power-down condition, then when one or both synthesizers are reactivated, the reference and main dividers restart in such a way as to avoid large random phase errors at the phase comparator.
CRA/CRB 0 1 Table 6 SR 0 1 Power-down modes
The device can be powered down either via pin HPD (active LOW = power-down) or via the serial bus (bits sPDA and sPDB, logic 0 = power-down).
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC VCC-DD Vn V3, 17 VGND Tstg Tamb HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. PARAMETER DC charge pump supply voltage with respect to AGND difference in voltage between VCC and VDD1, VDD2 DC voltage at pins 3 and 17 with respect to AGND MIN. -0.3 -0.3 -0.3 -0.3 MAX. +6.0 +6.0 +6.0 VDD1 + 0.3 VCC + 0.3 +0.3 +125 +85 V V V V V V C C UNIT
VDD1, VDD2 DC range of digital power supply voltage with respect to DGND
DC voltage at pins 1, 2, 5, 6, 8 to 15, 19 and 20 with respect to DGND -0.3 difference in voltage between AGND and DGND (these pins should be -0.3 connected together) storage temperature operating ambient temperature -55 -30
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Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
CHARACTERISTICS VDD1 = VDD2 = 2.7 to 5.5 V; VCC = 2.7 to 6.0 V; Tamb = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP.
UMA1015AM
MAX.
UNIT
Supplies; (VDD1, VDD2 and VCC) voltage doubler disabled, external supply on VCC VDD1, VDD2 digital supply voltage IDD1 + IDD2 total digital supply current from VDD1 and VDD2 VDD1 = VDD2 fXTAL = 12.8 MHz; both synthesizers on; VDD1 = VDD2 = 3 V fXTAL = 12.8 MHz; both synthesizers on; VDD1 = VDD2 = 5.5 V IDDpda, IDDpdb total digital supply current from VDD1 and VDD2 with one synthesizer in power-down mode fXTAL = 12.8 MHz; one synthesizer powered down; VDD1 = VDD2 = 3 V fXTAL = 12.8 MHz; one synthesizer powered down; VDD1 = VDD2 = 5.5 V fXTAL = 12.8 MHz; VHPD = 0 V; sPBF = 1; VDD1 = VDD2 = 3 V fXTAL = 12.8 MHz; VHPD = 0 V; sPBF = 1; VDD1 = VDD2 = 5.5 V both synthesizers powered down; VHPD = 0 V; sPBF = 0 VCC VDD both synthesizers on and in lock; fref = 12.5 kHz both synthesizers powered down 2.7 - - 8.7 5.5 - V mA
-
-
12.5
mA
-
5.0
-
mA
-
-
7.5
mA
IDD(xtal)
digital supply current from VDD1 with both synthesizers powered down and crystal buffer on digital supply current in power-down mode charge pump supply voltage charge pump supply current charge pump supply current in power-down mode
- - - 2.7 - -
0.5 - - - - -
- 1.15 60 6.0 25 25
mA mA A V A A
IDDpd VCC ICC ICCpd
Voltage doubler enabled IDD total digital supply current from VDD1 and VDD2 total digital supply current in power-down mode from VDD1 and VDD2 charge pump supply voltage fXTAL = 12.8 MHz; both synthesizers on and in lock; VDD1 = 3 V; fRF = 900 MHz both synthesizers powered down; VDD1 = 3 V; VHPD = 0 V; sPBF = 0 DC current drawn from VCC = 50 A; fRF > 100 MHz - 9.2 12 mA
IDDpd
-
0.25
0.4
mA
VCCvd
4.2
2VDD1 - 0.6 6.0
V
1997 Sep 03
8
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
SYMBOL PARAMETER CONDITIONS MIN. - - - - 300 1 - - - 10 1 - TYP.
UMA1015AM
MAX.
UNIT
RF main divider input; RFA and RFB fRF VRF(rms) RF input frequency RF input signal voltage (RMS value; AC coupled) Rs = 50 ; fRF = 400 to 1100 MHz Rs = 50 ; fRF = 50 to 80 MHz ZI CI Rpm input impedance (real part) input capacitance principle main divider ratio fRF = 1 GHz; indicative, not tested indicative, not tested 50 50 1100 250 400 400 - - 131071 MHz mV mV mV pF
Rs = 50 ; fRF = 80 to 400 MHz 150 225 - - 512
Reference divider input; fXTALIN fXTALIN reference input frequency from crystal 3 100 fXTALIN = 12.8 MHz; indicative, not tested indicative, not tested - - 8 - 35 500 - - 4095 - MHz mV k pF
VXTALIN(rms) sinusoidal input voltage (RMS value) ZI CI Rrd input impedance (real part) input capacitance reference divider ratio
Charge pump current setting resistor input; ISET VSET Icp voltage output on ISET charge pump sink or source current RSET = 12 to 60 k RSET = 15 k; CRA/CRB = logic 1; Icp = ISET x 24; Vcp = 0.4 V to VCC - 0.5 V RSET = 15 k; CRA/CRB = logic 0; Icp = ISET x 12; Vcp = 0.4 V to VCC - 0.5 V ILI charge pump off leakage current Vcp = 0.4 V to VCC - 0.5 V 1.1 V
Charge pump outputs; CPA and CPB 1.3 1.75 2.3 mA
0.7
0.9
1.2
mA
-5
1
+5
nA
Logic input signal levels; DATA, CLK, E and HPD VIH VIL Ibias CI HIGH level input voltage LOW level input voltage input bias currents input capacitance at logic 1 at logic 0 at logic 1 or logic 0 indicative, not tested 0.7VDD1 - -0.3 -5 - - - - 1 - VDD1 + 0.3 0.3VDD1 +5 - V V A pF
Port outputs/Out-of-lock; P0/OOL, P1, P2, P3 and fXTALO - open drain outputs VOL LOW level output voltage Isink < 0.4 mA 0.4 V
1997 Sep 03
9
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
SERIAL TIMING CHARACTERISTICS VDD1 = 3 V; Tamb = 25 C; unless otherwise specified. SYMBOL PARAMETER - 100 MIN. TYP.
UMA1015AM
MAX.
UNIT
Serial programming clock; CLK tr, tf Tcy tSTART tEND tW tSU;E tSU;DAT tHD;DAT input rise and fall times clock period 10 - - - - - - - 40 - - - - - - - ns ns
Enable programming; E delay to rising clock edge delay from last falling clock edge minimum inactive pulse width enable set-up time to next clock edge 40 -20 4000 20 ns ns ns ns
Register serial input data; DATA input data to clock set-up time input data to clock hold time 20 20 ns ns
handbook, full pagewidth
tEND tSU;DAT tHD;DAT Tcy tf tr tSU;E
CLK
DATA
MSB
LSB
ADDRESS
E tSTART
MGG524
tW
Fig.3 Serial bus timing diagram.
1997 Sep 03
10
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
TYPICAL PERFORMANCE CHARACTERISTICS
UMA1015AM
handbook, full pagewidth
12
MGK784
IDD (mA) 10
(1) (2)
8
(3)
6
4
2 2.5 (1) Tamb = +90 C.
3 (2) Tamb = +25 C.
3.5 (3) Tamb = -35 C.
4
4.5
5
VDD (V)
5.5
Fig.4 Typical IDD as a function of VDD with both synthesizers on and voltage doubler disabled.
handbook, full pagewidth
(2)
2.0 1.6 1.2 0.8 0.4 0
MGK783
ICPA (mA)
(1)
-0.4 -0.8 -1.2 -1.6 -2.0
(1) (2)
0
1
2
3
4
5
VCPA (V)
6
RSET = 15 k; CRA = 1.
(1) VCC = 2.7 V.
(2) VCC = 6.0 V.
Fig.5 Typical charge pump current as a function of CPA voltage with Tamb = 25 C.
1997 Sep 03
11
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
UMA1015AM
MGK782
handbook, full pagewidth
4 ICPA (nA) 2
(1)
0
(2) (3)
-2
-4
0 VCC = VDD = 6 V; RSET = 15 k;
1
2
3
4
5
VCPA (V)
6
CRA = 1.
(1) Tamb = +25 C.
(2) Tamb = -35 C.
(3) Tamb = +90 C.
Fig.6 Typical charge pump 3-state current as a function of CPA voltage.
handbook, full pagewidth
10
MGK779
VXTALIN (dBm) 0
+7
guaranteed area
-7
-10
-20
-30
(1) (2)
-40
-50
0
5
10
15
20
25
30 fXTALIN (MHz)
35
fXTALIN externally terminated by 50 load; AC-coupled.
(1) VDD = 5.5 V.
(2) VDD = 2.7 V.
Fig.7 Typical crystal input sensitivity as a function of input frequency with Tamb = 25 C.
1997 Sep 03
12
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
UMA1015AM
handbook, full pagewidth
10
MGK780
VXTALIN (dBm) 0
+7
guaranteed area
-7
-10
-20
-30
(1) (2) (3)
-40
0
5
10
15
20
25
30 fXTALIN (MHz)
35
fXTALIN externally terminated by 50 load; AC-coupled.
(1) Tamb = -35 C.
(2) Tamb = +25 C.
(3) Tamb = +90 C.
Fig.8 Typical crystal input sensitivity as a function of input frequency with VDD = 5.5 V.
handbook, full pagewidth
10
MGK781
VRF (dBm) 0
+5 +1
-3.5
guaranteed area -10
-13
-20
(1)
(2)
-30
0
100
200
300
400
500
600
700
800
900
1000
1100 fRF (MHz)
1200
RF input externally terminated by 50 load; AC-coupled.
(1) VDD = 5.5 V.
(2) VDD = 2.7 V.
Fig.9 Typical RF input sensitivity as a function of input frequency with Tamb = 25 C.
1997 Sep 03
13
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
UMA1015AM
handbook, full pagewidth
10
MGK778
VRF (dBm) 0
+5 +1
-3.5
guaranteed area -10
-13
-20
(1)
(2) (3)
-30
0
100
200
300
400
500
600
700
800
900
1000
1100 fRF (MHz)
1200
RF input externally terminated by 50 load; AC-coupled.
(1) Tamb = -35 C.
(2) Tamb = +25 C.
(3) Tamb = +90 C.
Fig.10 Typical RF input sensitivity as a function of input frequency with VDD = 5.5 V.
handbook, full pagewidth
6
MGK777
(1) (2)
VCC (V) 5.5
(3)
5
4.5
4 2.5 (1) Tamb = -35 C.
3 (2) Tamb = +25 C.
3.5 (3) Tamb = +90 C.
4
4.5
5
VDD (V)
5.5
Fig.11 Typical charge pump supply voltage as a function of VDD voltage with voltage doubler enabled.
1997 Sep 03
14
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
UMA1015AM
handbook, full pagewidth
1 0.5
(1)
2
(2)
0.2
(3)
5 10
+j 0 -j
0.2
0.5
1
2
5
10
10
0.2
5
0.5 1
2
MGK785
(1) Real part: 500 ; imaginary part: 1.4 pF; at 1.2 GHz. (2) Real part: 800 ; imaginary part: 1.1 pF; at 1.0 GHz.
(3) Real part: 830 ; imaginary part: 0.9 pF; at 800 MHz.
Fig.12 Typical RF input admittance (IC powered on).
handbook, full pagewidth
1 0.5 2
0.2
5 10
(2)
+j 0 -j
0.2
0.5
1
2
5
10
(1)
10
0.2
5
0.5 1 (1) Real part: 7.8 k; imaginary part: 0.9 pF; at 3 MHz.
2
MGK786
(2) Real part: 9.8 k; imaginary part: 1.0 pF; at 35 MHz.
Fig.13 Typical crystal input admittance (IC powered on).
1997 Sep 03
15
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
APPLICATION INFORMATION
UMA1015AM
handbook, full pagewidth
modulated audio
SPLITTER POWER AMPLIFIER
VOLTAGE CONTROLLED OSCILLATOR TRANSMIT PLL
LOW-PASS FILTER
MAIN DIVIDER A 959 MHz
PHASE COMPARATOR A
DUPLEX FILTER
TCXO
REFERENCE DIVIDER
UMA1015AM
914 MHz MAIN DIVIDER B
PHASE COMPARATOR B
RECEIVE PLL VOLTAGE CONTROLLED OSCILLATOR LOW-PASS FILTER
SPLITTER
LOW NOISE AMPLIFIER
856 MHz 1st IF AND REMAINDER OF RECEIVER CHAIN 1st MIXER to demodulation
MGG533
Fig.14 Typical application block diagram.
1997 Sep 03
16
ewidth
positive supply 3.9 k
1997 Sep 03
positive supply 10 k 18 27 k 15 k LED 1 20 19 18 17 16 UMA1015AM 6 7 8 13 12 11 CLK 1 k DATA 1 k 3-line bus positive supply
MGG534
15 120 100 nF 39 k 1 nF 56 nF control 56 56 k VCORx 1 nF RF output 18 1 nF 18 1 k 100 nF 856 MHz 18 18 1 nF 3.3 nF P1 P2 2 3 4 5 15 14 E VDD2 RFB AGND CPB VCC CPA VDD1 HPD 1 nF RFA DGND fXTALIN 1 nF P3 9 10 fXTALO 27 k 27 k positive supply 56 P0/OOL 100 nF ISET
Philips Semiconductors
27 k 15
100 nF
100 nF
39 1 k nF 56 nF
3.3 nF
control
56 k
VCOTx
1 nF
18
18
RF output
959 MHz
1 nF
audio modulation to 1st mixer
18
Low-power dual frequency synthesizer for radio communications
positive supply
to power amplifier
17 Fig.15 Typical CT1 application.
33
fOSC
100 nF
VTCXO
GND
Vctr
100 nF
10 k
Transmit frequency = 959 MHz. Receive frequency = 914 MHz. 1st IF = 58.1125 MHz. 2nd IF = 455 MHz. VCO sensitivity = 2 MHz/V. Channel spacing = 12.5 kHz. Charge pump gain (CPA = CPB) = 1 mA/cycle.
UMA1015AM
Product specification
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
PACKAGE OUTLINE SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm
UMA1015AM
SOT266-1
D
E
A X
c y HE vM A
Z
20
11
Q A2 pin 1 index A1 (A 3) Lp L A
1
e bp
10
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.20 0.13 D (1) 6.6 6.4 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT266-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-04-05 95-02-25
1997 Sep 03
18
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
UMA1015AM
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1997 Sep 03
19
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
UMA1015AM
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Sep 03
20
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
NOTES
UMA1015AM
1997 Sep 03
21
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
NOTES
UMA1015AM
1997 Sep 03
22
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer for radio communications
NOTES
UMA1015AM
1997 Sep 03
23
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
437027/1200/03/pp24
Date of release: 1997 Sep 03
Document order number:
9397 750 02704

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